Chip Sense / Tools / Export control simulator

Estimates only. These tools are illustrative what-if calculators for teaching and writing — not forecasts, quotes, fab plans, or legal/compliance advice. Defaults are curated teaching values; replace them with your own inputs.

Export control simulator

Toggle teaching rules derived from public export-control themes. Defaults align with the map’s export-controls scenario (EUV + DUV + service themes on). Results highlight which Chip Sense companies would be stressed in a what-if — not a legal determination.

Methodology

How to use

  1. Review Assumptions on the left. Amber badges are teaching estimates; they become Your input when you edit.
  2. Defaults match the map’s export-controls scenario (EUV, DUV, and service themes on).
  3. Toggle rules on or off to stress different companies in this teaching model.
  4. Use company chips in the results to open the map on that node — not legal advice.
  5. Read Estimated results on the right (~ means estimate). Use Reset or Methodology anytime.

Assumptions

Edit any field — values you change are treated as your input, not Chip Sense published facts.

Theme reference (not EAR text) — public EUV restriction coverage
Theme reference (not EAR text) — public DUV control discussions
Theme reference (not EAR text) — public BIS/EAR service-rule coverage
Theme reference (not EAR text) — illustrative memory-control scenario
Theme reference (not EAR text) — illustrative EDA-control scenario

Estimated results

Outputs use ~ / ranges on purpose. Basis: your current assumptions.

Illustrative severity

Estimate

moderate

Teaching score ~8 from active rule weights — not a real risk rating.

Stressed companies

Estimate

Links open the map on the export-controls scenario with that node selected.

Estimated effects

  • EUV lithography blocked: Leading-edge Chinese logic fabs stay on DUV-limited nodes in this teaching scenario.
  • EUV lithography blocked: Domestic substitution pressure rises for lithography and process modules.
  • Advanced DUV curtailed: Even mature leading-edge ramps at restricted fabs slow further.
  • Advanced DUV curtailed: ASML → SMIC-style equipment arcs read as disrupted on the map metaphor.
  • US-person service limits: Tool uptime and process bring-up at restricted fabs become harder in the teaching model.